NDLI: A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

Please wait, while we are loading the content...

2015 Symposium on VLSI Technology (VLSI Technology)

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

2013 Symposium on VLSI Technology

2012 Symposium on VLSI Technology (VLSIT)

2011 Symposium on VLSI Technology - Digest of Technical Papers

2010 Symposium on VLSI Technology

2009 Symposium on VLSI Technology

2008 Symposium on VLSI Technology

2007 IEEE Symposium on VLSI Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

1997 Symposium on VLSI Technology

1996 Symposium on VLSI Technology. Digest of Technical Papers

1995 Symposium on VLSI Technology. Digest of Technical Papers

Proceedings of 1994 VLSI Technology Symposium

Symposium 1993 on VLSI Technology

1992 Symposium on VLSI Technology Digest of Technical Papers

1991 Symposium on VLSI Technology

Digest of Technical Papers.1990 Symposium on VLSI Technology

ECR position etching for high selectivity and high-rate N+poly-Si patterning

A new interlayer formation technology for completely planarized multilevel interconnection by using LPD

Selective and nonselective deposition of aluminum by LPCVD using DMAH and microregion observation of single crystal aluminum with scanning μ-RHEED microscope

KrF excimer laser lithography with high sensitivity positive resist and high power laser

A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography

A high performance 16-Mb DRAM technology

A 1.28 $μm^{2}$ bit-line shielded memory cell technology for 64 Mb DRAMs

A ferroelectric DRAM cell for high density NVRAMs

Buried bit-line cell for 64 Mb DRAMs

A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load

A high-performance stacked-CMOS SRAM cell by solid phase growth technique

TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

A manufacturable 2.0 micron pitch three-level-metal interconnect process for high performance 0.8 micron CMOS technology

Suppressing stress-induced and electromigration failures with Al/Al stacked structure

An analytical model for linewidth-dependent electromigration lifetime in VLSI interconnects

Effect of stress in passivation layer on electromigration lifetime for vias

Improved yield and reliability in aluminum interconnects through fluorine incorporation

Electromigration characteristics of via chains for multilayered metallization

Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise

A highly reliable 0.3 μm n-channel MOSFET using poly spacers

A high speed and high reliability MOSFET utilizing an auxiliary gate

A new structural approach for reducing hot carrier generation in deep submicron MOSFETs

A fundamental performance limit of optimized 3.3 V subquarter micron fully overlapped LDD MOSFETs

SiGe-base PNP transistors fabricated with n-type UHV/CVD LTE in a `No Dt' process

63-75 GHz $f_{T}$ SiGe-base heterojunction bipolar technology

A 26 ps self-aligned epitaxial silicon base bipolar technology

STRIPE-a high-speed VLSI bipolar technology featuring self-aligned single-poly base and submicron emitter contacts

Perimeter and plug effects in deep sub-micron polysilicon emitter bipolar transistors

The improvement of Al-Si-Cu alloy interconnects by hafnium and boron addition

Superconducting interconnects for VLSI multi-chip system integration

Photo assisted LPCVD TiN for deep submicron contacts using organo-titanium compound

Formation of ultra-shallow low-reverse current $n^{+}p$ junctions by 450°C furnace annealing

Very shallow $p^{+}-n$ junctions and subquarter micron gate p-channel MOSFETs

Two-dimensional simulation of band-to-band tunneling in an LDD-MOSFET: explanation of experimental results and prediction of new phenomena

Drain-structure design for reduced band-to-band and band-to-defect tunneling leakage

A spill over effect of avalanche generated electrons in buried pMOSFETs

A new MOSFETs degradation induced by gate current in off-state condition

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

A novel CBi-CMOS technology by DIIP process

Lower submicron FCBiMOS (fully complementary BiMOS) process with RTP and MeV implanted 5 GHz vertical PNP transistor

Merged complementary BiCMOS for logic applications

New well structure for deep sub-μm CMOS/BiCMOS using thin epitaxy over buried layer and trench isolation

SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL

0.6 μm, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications

A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices

BiCMOS gate performance optimization using a unified delay model

A new SOL fabrication technique for ultrathin active layer of less than 80 nm

Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology

A utility-based integrated process simulation system

On-line process optimization and control using the sequential design of experiments

Continuous diagnosis of low-pressure chemical vapor deposition reactors using evidence integration

A novel technique for in-line monitoring of micro-contamination and process induced damage

Non-invasive process temperature monitoring using laser-acoustic techniques

Non-invasive silicon temperature measurement by infrared transmission for rapid thermal processing applications

Device performance analysis using Monte-Carlo simulator for SOI MOS transistors on solid-phase-recrystallized silicon films

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in $BF_{2}$ implanted P+ gate p-channel MOSFETs

A new aspect on mechanical stress effects in scaled MOS devices

Tungsten silicide/titanium nitride compound gate for submicron CMOSFET

Role of surface passivation in the integrated processing of MOS structures

Dielectric breakdown and current conduction of oxide/nitride/oxide multi-layer structures

Reliability degradation mechanism of the ultra-thin tunneling oxide by the post-annealing

Mobile ion gettering in passivated p+ polysilicon gates

A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell

Process technologies for a 16 ns high speed 1 Mb CMOS EPROM

A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM

Analysis of an ONO gate film effect on n- and p-MOSFET mobilities

1987 Symposium on VLSI Technology. Digest of Technical Papers

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in