NDLI: 0.6 /spl mu/m Pitlch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG For Sub-quarter Micron CMOS Technology

Please wait, while we are loading the content...

2015 Symposium on VLSI Technology (VLSI Technology)

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

2013 Symposium on VLSI Technology

2012 Symposium on VLSI Technology (VLSIT)

2011 Symposium on VLSI Technology - Digest of Technical Papers

2010 Symposium on VLSI Technology

2009 Symposium on VLSI Technology

2008 Symposium on VLSI Technology

2007 IEEE Symposium on VLSI Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

1997 Symposium on VLSI Technology

1997 symposium on VLSI technology [front matter and table of contents]

The 300mm Technology Current Status And Future Prospect

Keeping Both Sides Winning: Wafer Fabrication Equipment Suppliers And Semiconductor Manufacturers In The Year 2000 And Beyond

Highly Manufacturable 1Gb SDRAM

A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs

0.18 /spl mu/m CMOS Technology For High-performance, Low-power, And RF Applications

Uniformity And Reliability Of 1.5 nm Direct Tunneling Gate Oxide MOSFETs

A Fully Printable, Self-aligned And Planarized Stacked Capacitor DRAM Cell Technology For 1Gbit DRAM And Beyond

A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)

Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM

0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices

Modeling Of Chemical Mechanical Polishing Process For Three-dimensional Simulation

Dielectric Planarization Using Mn203 Slurry

Scaling Inter-poly Contacts For 0.25 /spl mu/m And Below With WSI/sub x/ Polishing

Copper Integration In Self Aligned Dual Damascene Architecture

A 5-mask CMOS Technology

A Very High Performance, Epi-free, And Manufacturable 3.3 V 0.35 /spl mu/m BiCMOS Technology For Wireless Applications

A Novel Environmentally-friendly Corrosion-free Post-stripping Rinsing Procedure After Solvent Strip

New Insight On Electromigration Failure Mechanism And Its Impact On Design Guidelines

Physical Model For Contact Degradation At High Current Densities

Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness

An Advanced 2.5nm Oxidized Nitride Gate Dielectric For Highly Reliable 0.25/spl mu/m MOSFETs

A 0.18/spl mu/m CMOS Process Using Nitrogen Profile-engineered Gate Dielectrics

A Novel Low-temperature Gate Oxynitride For CMOS Technologies

Ultra-thin Silicon Nitride Gate Dielectric For Deep-sub-micron CMOS Devices

Interconnect Scaling Scenario Using A Chip Level Interconnect Model

A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor

A Novel Copper Reflow Process Using Dual Wetting Layers

Ultra-low Resistance Diret~ Contact Cu Via technology Using In-situ Chemical Vapor Cleamng

A Novel CMOS Compatible Stacked Floating Gate Device Using TiN As A Control Gate

A Novel Flash Memory Device With S Plit Gate Source Side Injection And 0N0 Charge Storage Stack (SPIN)

Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology

A New Flash Architecture With A 5.8/spl lambda//sup 2/ Scalable AMG Flash Cell

Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs

Advanced Gate-stack Architecture For Low-voltage Dual-workfunction CMOS Technologies With Shallow Trench Isolation

A mesh-arrayed MOSFET (MA-MOS) for high-frequency analog applications

A 5.5/spl mu/m CMOS Image Sensor Cell Utilizing A Buried Reset Channel

Integration Of Ultra-low-k Xerogel Gapfill Dielectric For high Performance Sub-o.18 /spl mu/m Interconnects

0.6 /spl mu/m Pitlch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG For Sub-quarter Micron CMOS Technology

Integration Of Thermally Stable, Low-k AF4 Polymer For 0.18 /spl mu/m Interconnects And Beyond

Implication And Solutions For Joule Heating In High Performance Interconnects Incorporating Low-k Dielectrics

Transient-enhanced Diffusion Of Iridium And Its Eflects On Electrical Characteristics Of Deep Sub-micron nMOSFETs

Channel Profile Control Based On Transient-enhanced-diffusion Suppression By RTA For 0.18 /spl mu/m Single Gate CMOS

Boron Implanted Shallow Junction Formation By High-temperature/ Short-time/high-ramping-rate(400/spl deg/C/sec) RTA

Manufacturable Shallow-junction Processes To Overcome Defect Formation And Dopant Reactions For Sub-0.18/spl mu/m CMOS Technologies

A Highly Reliable 0.35/spl mu/m Field-shield Body-tied SOI Gate Array For Substrate-bias-effect Free Operation

An Advanced Ge Pre-amorphization Salicide Technology For Sub-quarter-micrometer SOI CMOS Devices

A Novel Technique For 3-d Integration: Ge-seeded Laterally Crystallized TFTs

Correlation Between Low-frequency Noise Overshoot In SOI MOSFETs And Frequency Dependence Of Floating Body Effect

0.25 /spl mu/m salicide CMOS Technology Thermally Stable Up To 1,000/spl deg/C With High TDDB Reliability

Salicides for 0.10 /spl mu/m gate lengths: a comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co process

Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology

Gate Electrode Engineering By Control Of Grain Growth For High Performance And High Reliable 0.18/spl mu/m Dual Gate CMOS

R-1 Merged Logic And DRAM

R-2 The Interconnect Crisis

R-3 Ferroelectric Memory

R-4 Surface Control And Thin Gate Oxides

A New Oxide Damage Characterization Technique For Evaluating Hot Carrier Reliability Of Flash Memory Cell After P/E Cycles

A Novel SONOS Structure For Nonvolatile Memories With Improved Data Retention

A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories

A Novel High K Inter-poly Dielectric(IPD), A1/sub 2/O/sub 3/ For Low Voltage/high Speed Flash memories: erasing in msecs at 3.3V

Impact Of Trench Sidewall Interface Trap In Shallow Trench Isolation On Junction Leakage Current Characteristics For Sub-0.25 /spl mu/m CMOS Devices

A very simple trench isolation (VSTI) technology with chemo-mechanically polished (CMP) substrate Si

Mechanical Stress Induced MOSFET Punch-through And Process Optimization For Deep Submicron TEOS-O/sub 3/ Filled STI Device

A Robust 0.15/spl mu/m CMOS Technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation

Deep-UV Lithographic Approaches For 1 Gb DRAM

Fabrication Of 100 nm pMOSFETS With Hybrid AFW / STM Lithography

Fabrication Of 0.06 /spl mu/m Poly-si Gate Using Duv Lithography With A Designed Si/sub x/O/sub y/N/sub z/ Film As An Arc And Hardmask

Technology And Power-speed Trade-offs In Quantum-dot And Nano-crystal Memory Devices

Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs

Low-damage ECR-plasma-etching technique for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) capacitor for FeRAM devices

A 1T/1C Ferrodectric RAM Using A Double-level Metal Process For Highly Scalable Nonvolatile Memory

Computationally Efficient Ferroelectric Capacitor Model For Circuit Simulation

A New Dielectric Breakdown Mechanism In Silicon Dioxides

Energy funnels - A new oxide breakdown model

Charging And Intrinsic-leakage Current Peaks In Thin Silicon-dioxide Films

Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/)

Cylindrical Full Metal Capacitor Technology For High-speed Gigabit DRAMs

The Simplest Stacked BST Capacitor For The Future DRAMs Using A Novel Low Temperature Growth Enhanced Crystallization

A Novel Merged Gain Cell For Logic Compatible High Density DRAMs

Suppression Of Bit-line-induced Disturbance In SOI DRAM/SRAM Cells By Bipolar Embedded Source Structure (BESS)

1996 Symposium on VLSI Technology. Digest of Technical Papers

1995 Symposium on VLSI Technology. Digest of Technical Papers

Proceedings of 1994 VLSI Technology Symposium

Symposium 1993 on VLSI Technology

1992 Symposium on VLSI Technology Digest of Technical Papers

1991 Symposium on VLSI Technology

Digest of Technical Papers.1990 Symposium on VLSI Technology

1987 Symposium on VLSI Technology. Digest of Technical Papers

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in