NDLI: An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells

Please wait, while we are loading the content...

2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

2013 Symposium on VLSI Circuits

2012 Symposium on VLSI Circuits (VLSIC)

2011 Symposium on VLSI Circuits - Digest of Technical Papers

2010 Symposium on VLSI Circuits

2009 Symposium on VLSI Circuits

2008 IEEE Symposium on VLSI Circuits

2007 IEEE Symposium on VLSI Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Symposium 1989 on VLSI Circuits

Fuzzy logic hardware systems

High performance VLSI processor architectures

High performance BiCMOS circuit technology VLSI gate arrays

SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit

CMOS subnanosecond true-ECL output buffer

A versatile data-transfer control unit for a parallel processor system

ALTICS: an advanced timing analysis system for VLSI

A review of superconducting three-terminal devices

A sub-ns clock josephson 4b processor

An experimental low temperature DRAM

Soft-error characteristics in bipolar memory cells with small critical charge

An /spl alpha/-immune, 2V supply voltage SRAM using polysilicon PMOS load cell

High-reliability and high-speed design of 1Mb CMOS SRAM with 0.5/spl mu/m devices

A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range

A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM

A 68ns 4Mbit CMOS EPROM with high noise immunity design

A self-timed dynamic sensing scheme for 5V only multi-Mb flash E/sup 2/PROMs

A 1.7 volts operating CMOS 64K bit E/sup 2/ PROM

An eyperimental 1Mb cache DRAM with ECC

Circuit design of a 9ns-HIT-delay 32K byte cache macro

Mappable memory subsystem for high speed applications

High-performance analog-to-digital converters

Improving bandwidth and error rate in flash converters

An 8-bit 20 MS/s CMOS A/D converter with 59 mW power consumption

Analog-to-digital converter with non-linear capacitor compensation

An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells

An 8 bit, 200 MHz BiCMOS comparator

A CMOS 70 MB/S(RZ) 16x16 crosspoint switch for ternary encoded signals

A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs

A 4ns 16k BiCMOS SRAM

11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces

Automatic gain control (AGC) circuit for high density BiCMOS SRAM

"A 1.6ns 64kb ECL RAM with 1K gate logic"

High reliability CMOS SRAM with built-in soft defect detection

A multi bit test trigger circuit for Mbit SRAM's

A 36μa 4MB PSRAM with quadruple array operation

Design of optically coupled three dimensional common memory for parallel processor system

A monolithically integrated fiber-optic front-end receiver in GaAs Si technology

A 26 dB, 1.2 GHz wideband GaAs MESFET variable gain amplifier

A low-poswer wide-band amplifier using a new parasitic capacitance compensation technique

A 2 GHz clock direct frequency synthesiser

A low power time-multiplexed SC speech spectrum analyzer

A TV(UHF/VHF)/Fm/AM compatible Bi-CMOS 1GHz single chip PLL IC

Jitter analysis of high speed sampling systems

Programmable vector-matrix multipliers for artificial neural networks

The stabilized reference-line (SRL) technique for scaled DRAMs

A novel memory cell architecture for high-density DRAMs

Decoded-source sense amplifier for high-density DRAMs

A 50MHz 8Mb video RAM with a column direction drive sense amplifier

An experimental 27w 1Mb CMOS high-speed DRAM

A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier

A speed enhancement DRAM array architecture with embedded ECC

An expermental 16Mb DRAM with reduced peak-current noise

A modularized speech recognition processor LSI with a highly parallel structure

Design of an outline font rasterizing LSI

A data flow image compression processor

An on-chip smart memory for a data flow CPU

A 100 mega-access matching memory for a data-driven microprocessor

High-performance multiple-valued radix-2 signed-digit multiplier and its application

Ultra-highly parallel residue arithmetic VLSI system

Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol

Symposium 1988 on VLSI Circuits

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in