NDLI: On functional entropy

Please wait, while we are loading the content...

2015 IEEE International Symposium on Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic

2013 IEEE 43rd International Symposium on Multiple-Valued Logic

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

2011 41st IEEE International Symposium on Multiple-Valued Logic

2010 40th IEEE International Symposium on Multiple-Valued Logic

2009 39th International Symposium on Multiple-Valued Logic

38th International Symposium on Multiple Valued Logic (ismvl 2008)

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

Proceedings. 34th International Symposium on Multiple-Valued Logic

33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.

Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic

Proceedings 31st IEEE International Symposium on Multiple-Valued Logic

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)

Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)

Proceedings 1997 27th International Symposium on Multiple- Valued Logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Proceedings 25th International Symposium on Multiple-Valued Logic

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

Design of multiple-valued linear digital circuits for highly parallel unary operations

Design of set-valued logic networks for wave-parallel computing

Impact of interconnection-free biomolecular computing

CMOS implementation and fabrication of the pseudo analog neuron

Lukasiewicz' insect: the role of continuous-valued logic in a mobile robot's sensors, control, and locomotion

Functional completeness and weak completeness in set logic

Current-mode CMOS Galois field circuits

An algebra for current-mode CMOS multivalued circuits

Calculation of ternary mixed polarity function vector

Decimal addition and subtraction units using the p-valued decimal signed-digit number representation

Multiple-valued logic functions represented by TSUM, TPRODUCT, NOT and variables

A basis for the comparison of binary and m-valued current mode circuits: the multioperand addition with redundant number systems

Systematic construction of natural deduction systems for many-valued logics

Algorithm and implementation of a learning multiple-valued logic network

Algebraic properties of a learning multiple-valued logic network

An inexact reasoning technique using linguistic rule matrix transformations

A representation of approximate reasoning with analogy

Multiple valued logic: current-mode CMOS circuits

A multiple-valued content-addressable memory using logic-value conversion and threshold functions

Multiple-valued logic computation circuits using micro- and nanoelectronic devices

Series resonant tunneling diodes as a two-dimensional memory cell

Design and examination of a multiple-valued flip-flop circuit with stair shaped I-V curved device as a coupling element

Dreams for new-device-based superchips: from transistors to enzymes

EXORCISM-MV-2: minimization of exclusive sum of products expressions for multiple-valued input incompletely specified functions

A fast algorithm for the disjunctive decomposition of m-valued functions. II. Time complexity analysis

A fast algorithm for the disjunctive decomposition of m-valued functions. I. The decomposition algorithm

Some results on the decision and construction for Sheffer functions in partial k-valued logic

Semirigid sets of quasilinear clones

On functional entropy

A repairable and diagnosable cellular array on multiple-valued logic

A method of test pattern generation for multiple-valued PLAs

Novel CMOS scan design for VLSI testability

Synthesis and design automation of analog fuzzy logic VLSI circuits

Single-chip realization of a fuzzy logic controller with neural network structure (NNFLC)

On the definition of modal operators in fuzzy logic

Minimal resolution proof systems for finitely-valued Lukasiewicz logics

Signed formulas and annotated logics

Three-valued nonmonotonic logic

A canonical disjunctive form of extended Kleene-Stone logic functions

Gate model networks for minimization of multiple-valued logic functions

Entropic minimization of multiple-valued functions

Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

Fast synthesis for ternary Reed-Muller expansion

Multiple-valued logic design tools

Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in