NDLI: Evaluation and reduction of charging damage during metal etching

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2003 8th International Symposium Plasma- and Process-Induced Damage.

7th International Symposium on Plasma- and Process-Induced Damage

2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538)

2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479)

1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)

1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)

Shift of paradigms in microelectronics

Minimizing charge-up damage during dielectric etchers hardware and process development stages

Impact of reactor- and transistor-type on electron shading effects

Study of the influence of process parameters on gate oxide degradation during contact etching in MERIE and HDP reactors

Antenna ratio definition for VLSI circuits [plasma etch damage]

On the dependence of plasma-induced charging damage on antenna area

Effect of plasma density and uniformity, electron temperature, process gas, and chamber on electron shading damage

Evaluation and reduction of electron shading damage in high temperature etching

The sensitivity of electron shading damage to electron temperature, electron density and the plasma-to-wafer electron energy threshold

Pulse-time-modulated plasma etching for high performance polysilicon patterning on thin gate oxides

Compounding effects of UV exposure, ion bombardment, electron shading and plasma charging in a high density plasma poly etcher

Plasma process induced degradation of thin inter-polysilicon dielectric layers

Evaluation of rapid thermal nitrided ONO interpoly dielectric resistance to plasma process-induced damage

Plasma induced damage from HDP process on the ultra-thin gate oxide

Effect of the pattern structures on the charging damage during metal etching

Annealing of plasma charging damage and residual degradation in MOS transistors

Application of the deuterium sintering process to improve the device design rule in reducing plasma induced damages

A study of effects of plasma-induced charging damage on hot-carrier lifetime using pre-stressed data

Plasma damage impact on nMOS electrical characteristics during a CCS stress

Plasma damage evaluation using matched transistors and determination of damage prevention options

Evaluation of charging damage caused by the pattern structures during Al etching

Plasma damage during dielectric etch in high density plasma etcher

The prevention of charge damage on thin gate oxide from high density plasma deposition

Charge-up damage of dual gate transistor during RF pre-cleaning of metal contact before barrier metal deposition

Effects of processing pressure on device damage in RF biased ECR CVD

Reduction and non-uniformity of high density plasma process induced electrical degradation in MOS devices

Comparison of CHARM-2 and surface potential measurement to monitor plasma induced gate oxide damage

A method for reducing notching and electron shading damage in a continuous wave ECR metal etcher

Evaluation of charging damage in a plasma doping system

Process-induced damage by a low energy neutral beam source [etching/cleaning]

Plasma damage characterization of the Lam TCP/sup TM/ 9600PTX high-density, inductively coupled metal etcher and microwave asher

Characterization of ion implanter electron flood guns using charge pumping and threshold voltage measurements

Hardware and process dependence of electron shading damage in a high density plasma oxide etch tool

Detection of magnetically induced plasma charging from passivation level processing using corona-oxide-semiconductor techniques

Ultra-thin oxynitride gate dielectrics for 0.18 /spl mu/m CMOS and beyond

Relationship between plasma damage, SILC and gate-oxide reliability

Plasma-induced charging damage in ultrathin (3 nm) nitrided oxides

Control of performance degradation induced by contact etching for a ferroelectric capacitor using a pulsed-power inductively coupled plasma

Plasma diagnosis and charging damage

Suppression of topography dependent charging using a phase-controlled pulsed inductively coupled plasma

Effect of wafer bias frequency on microtrenching during high selective gate etching

Evaluation and reduction of charging damage during metal etching

Reduction of charging damage of gate oxide by time modulation bias method

Damascene copper integration

Comparison between gate oxide degradation induced by copper dual damascene and conventional aluminum processes

Process-induced damage in a dual-oxide (3.5/6.8 nm) 0.18-/spl mu/m copper CMOS technology

Charging protection and degradation by antenna environment on NMOS and PMOS transistors

Effect of low temperature deuterium annealing on plasma process induced damage

Plasma vacuum ultraviolet emission in a high density etcher

Alternative interpretation of plasma processing damage data to facilitate comparisons between oxide etchers

Device effects and charging damage: correlations between SPIDER-MEM and CHARM/sup R/-2

Dependence of plasma damage on density and T/sub e/ in a decoupled plasma source metal etcher

Fast hot-carrier aging method of charging damage measurement

1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100)

2nd International Symposium on Plasma Process-Induced Damage

Proceedings of 1st International Symposium on Plasma Process-Induced Damage

Evaluation and reduction of charging damage during metal etching

Content Provider	IEEE Xplore Digital Library
Author	Omoto, Y. Ono, T. Watanabe, S. Yoshioka, K. Mizutani, T. Tokunaga, T.
Copyright Year	1999
Description	Author affiliation: Hitachi Ltd., Yamaguchi, Japan (Omoto, Y.)
Abstract	In order to evaluate and find ways to reduce charging damage during metal interconnect etching, a circuit model including electron cyclotron resonance (ECR) plasma, devices on the wafer and bias power source is developed. As the interlayer dielectric thickness increases and capacitance decreases, AC stress current during main etching must be taken into account. The macroscopic charging due to peripheral etching can be reduced by lowering the bias frequency and magnetic field strength on the wafer. The microscopic charging caused by electron shading is expressed by this circuit model and its reduction by time modulation (TM) biasing is shown.
Starting Page	163
Ending Page	166
File Size	210297
Page Count	4
File Format	PDF
ISBN	0965157733
DOI	10.1109/PPID.1999.798839
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	American Vacuum Soc.
Subject Keyword	Etching Semiconductor device modeling Electrons Integrated circuit interconnections RLC circuits Cyclotrons Magnetic resonance Plasma applications Plasma devices Plasma sources
Content Type	Text
Resource Type	Article

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