NDLI: CMOS image sensor wafer-level packaging

Content Provider	IEEE Xplore Digital Library
Author	Matthias, T. Kreindl, G. Dragoi, V. Wimplinger, M. Lindner, P.
Copyright Year	2011
Description	Author affiliation: EV Group, DI Erich Thallner Strasse 1, 4782, Sankt Florian/Inn, Austria (Matthias, T.; Kreindl, G.; Dragoi, V.; Wimplinger, M.; Lindner, P.)
Abstract	This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.
Starting Page	1
Ending Page	6
File Size	2923846
Page Count	6
File Format	PDF
ISBN	9781457717703
e-ISBN	9781457717697
e-ISBN	9781457717680
DOI	10.1109/ICEPT.2011.6067039
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lenses Cameras Bonding Sensors Coatings CMOS integrated circuits wafer-level processing and integration CIS module BSI wafer-level camera wafer-level optics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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