NDLI: Design and Implementation of a GALS Adapter for ANoC Based Architectures

Content Provider	IEEE Xplore Digital Library
Author	Thonnart, Y. Beigne, E. Vivet, P.
Copyright Year	2009
Abstract	As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local programmable clock generator for the IP unit. The GALS adapter has been implemented in a ST 65nm technology in standard-cell based design. It is provided as a hard-macro for easy IP integration, can generate 256 clock frequencies from 25 MHz to 1 GHz, and achieves 500 MHz nominal throughput from a clocked domain to a QDI asynchronous logic NoC.
Starting Page	13
Ending Page	22
File Size	610398
Page Count	10
File Format	PDF
ISBN	9781424439331
ISSN	15228681
DOI	10.1109/ASYNC.2009.13
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Network-on-a-chip Timing Throughput Delay Computer architecture Synchronization Frequency Integrated circuit interconnections Quality of service GALS architectures Asynchronous logic circuits
Content Type	Text
Resource Type	Article

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Design and Implementation of a GALS Adapter for ANoC Based Architectures