NDLI: Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes

Content Provider	ACM Digital Library
Author	Tang, Aoxiang Gao, Xun Chen, Lung-Yen Jha, Niraj K.
Copyright Year	2016
Abstract	The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.
Starting Page	1
Ending Page	21
Page Count	21
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2795231
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	12
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-03-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	FinFETs PVT variations SRAM Parametric yield Statistical analysis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

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