NDLI: Coding scheme for low energy consumption fault-tolerant bus

Content Provider	IEEE Xplore Digital Library
Author	Rossi, D. van Dijk, V.E.S. Kleihorst, R.P. Nieuwland, A.H. Metra, C.
Copyright Year	2002
Description	Author affiliation: Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy (Rossi, D.)
Abstract	We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses using Hamming single error correcting codes. We show that no power saving is possible by choosing between different optimal Hamming codes with the same redundancy. We then propose a new coding scheme which provides a reduction of the energy consumption and power-delay product of over the 11.5% and 45%, respectively, with respect to the optimal (7,4) Hamming code, for a 0.13/spl mu/m CMOS technology bus.
Starting Page	8
Ending Page	12
File Size	308101
Page Count	5
File Format	PDF
ISBN	0769516416
DOI	10.1109/OLT.2002.1030176
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-07-10
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Fault tolerance Error correction codes Capacitance Crosstalk CMOS technology Testing Wires Power dissipation Fault detection
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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