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  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
  3. Custom-Enabled System Architectures for High End Computing
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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Table of contents - IWIA 2004
Preface
Program Committee
Direct Instruction Wakeup for Out-of-Order Processors
A Super Instruction-Flow Architecture for High Performance and Low Power Processors
Power-Aware Register Renaming in High-Performance Processors Power-Aware Register Renaming in High-Performance Processors
Custom-Enabled System Architectures for High End Computing
A New Memory Module for COTS-Based Personal Supercomputing
Fault-Tolerant Adaptive Deadlock-Recovery Routing for k-ary n-cube Networks
GXP : An Interactive Shell for the Grid Environment
Array Data Dependence Testing with the Chains of Recurrences Algebra
Memory Management for Data Localization on OSCAR Chip Multiprocessor
Implementation Details and Evaluation of a New Exact and Fast Test for Array Data Dependence Analysis Based on Simplex Method
Large-Scale 3-D Fluid Simulations for Implosion Hydrodynamics on the Earth Simulator
Highly Functional Memory Architecture for Large-Scale Data Applications
Parallel Processing using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor
Of Piglets and Threadlets: Architectures for Self-Contained, Mobile, Memory Programming
Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor
YAWARA: A Meta-Level Optimizing Computer System
Author index
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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Custom-Enabled System Architectures for High End Computing

Content Provider IEEE Xplore Digital Library
Author Sterling, T. Kogge, P.
Copyright Year 2004
Description Author affiliation: California Inst. of Technol. (Sterling, T.)
Abstract The US Federal Government has convened a major committee to determine future directions for government sponsored high end computing system acquisitions and enabling research. The High End Computing Revitalization Task Force was inaugurated in 2003 involving all Federal agencies for which high end computing is critical to meeting mission goals. As part of the HECRTF agenda, a multi-day community wide workshop was conducted involving experts from academia, industry, and the national laboratories and centers to provide the broadest perspective on important issues related to the HECRTF purview. Among the most critical issues in establishing future directions is the relative merits of commodity based systems such as clusters and MPPs versus custom system architecture strategies. This paper presents a perspective on the importance and value of the custom architecture approach in meeting future US requirements in supercomputing. The contents of this paper reflect the ideas of the participants of the working group chartered to explore custom enabled system architectures for high end computing. As in any such consensus presentation, while this paper captures the key ideas and tradeoffs, it does not exactly match the viewpoint of any single contributor, and there remains much room for constructive disagreement and refinement of the essential conclusions
Starting Page 30
Ending Page 39
File Size 124656
Page Count 10
File Format PDF
ISBN 076952205X
ISSN 15373223
DOI 10.1109/IWIA.2004.10014
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2004-01-12
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Computer architecture High performance computing Concurrent computing US Government Microprocessors Computer networks Time sharing computer systems Memory management Laboratories Costs
Content Type Text
Resource Type Article
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