NDLI logo
  • Content
  • Similar Resources
  • Metadata
  • Cite This
  • Log-in
  • Fullscreen
Log-in
Do not have an account? Register Now
Forgot your password? Account recovery
  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
  3. Preliminary evaluation of a binary translation system for multithreaded processors
Loading...

Please wait, while we are loading the content...

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Power and performance fitting in nanometer design
Reducing power with an L0 instruction cache using history-based prediction
Tight non-linear loop timing estimation
Exploring advanced architectures using performance prediction
Trading bandwidth for latency: managing continuations through a carpet bag cache
Architecture and compiler co-optimization for high performance computing
Multigrain parallel processing for JPEG encoding on a single chip multiprocessor
Branch classification to control instruction fetch in simultaneous multithreaded architectures
Preliminary evaluation of a binary translation system for multithreaded processors
A low latency high bandwidth network interface prototype for PC cluster
Design and implementation of interrupt packaging mechanism
A networking oriented data-driven processor: CUE
Author index
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

Similar Documents

...
Dynamic thread resizing for speculative multithreaded processors

Article

...
Thread Merging Schemes for Multithreaded Clustered VLIW Processors

Article

...
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind

Article

...
The effects of STEF in finely parallel multithreaded processors

Article

...
Compiling C for the EARTH multithreaded architecture

Article

...
Evaluation of the performance of multithreaded Cilk runtime system on SMP clusters

Article

...
Accelerated Deterministic Multithreading for Multichannel Video Decoder

Article

...
Programming Abstractions and Toolchain for Dataflow Multithreading Architectures

Article

...
A Binary Translation System for Multithreaded Processors and its Preliminary Evaluation (2001)

Article

Preliminary evaluation of a binary translation system for multithreaded processors

Content Provider IEEE Xplore Digital Library
Author Ootsu, K. Yokota, T. Ono, T. Baba, T.
Copyright Year 2002
Description Author affiliation: Dept. of Inf. Sci., Utsunomiya Univ., Tochigi, Japan (Ootsu, K.; Yokota, T.; Ono, T.; Baba, T.)
Abstract Thread level parallelism (TLP) is a key technology for next-generation high performance processors. Although it provides higher processing capability, the loss of compatibility with existing processors is a crucial issue. This research is motivated by the following two points: (1) TLP requires multithread programming which is rather difficult for ordinary programmers, or complex compilation technologies that can exploit multithread parallelism, and (2) existing binary codes should be executed efficiently on multithreaded processors. In this paper, we first propose a binary translation system, that translates existing binary codes to multithreaded ones and optimizes them dynamically during execution. The system inputs the original binary codes and translates them to internal RTL representation. It analyzes the structure of the program and applies multithreading to loop bodies in a thread pipelining manner. A pilot binary translator, that is a part of the proposed system, was built for the sake of preliminary evaluation. Evaluation results illustrate effectiveness of the system.
Starting Page 77
Ending Page 84
File Size 1396609
Page Count 8
File Format PDF
ISBN 0769516351
ISSN 15373223
DOI 10.1109/IWIA.2002.1035021
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2002-01-11
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Yarn Binary codes Multithreading Pipeline processing Programming profession Runtime Instruction sets VLIW Information science Parallel programming
Content Type Text
Resource Type Article
  • About
  • Disclaimer
  • Feedback
  • Sponsor
  • Contact
About National Digital Library of India (NDLI)
NDLI logo

National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.

Learn more about this project from here.

Disclaimer

NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.

Feedback

Sponsor

Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.

Contact National Digital Library of India
Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302
See location in the Map
03222 282435
Mail: support@ndl.gov.in
Sl. Authority Responsibilities Communication Details
1 Ministry of Education (GoI),
Department of Higher Education
Sanctioning Authority https://www.education.gov.in/ict-initiatives
2 Indian Institute of Technology Kharagpur Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project https://www.iitkgp.ac.in
3 National Digital Library of India Office, Indian Institute of Technology Kharagpur The administrative and infrastructural headquarters of the project Dr. B. Sutradhar  bsutra@ndl.gov.in
4 Project PI / Joint PI Principal Investigator and Joint Principal Investigators of the project Dr. B. Sutradhar  bsutra@ndl.gov.in
Prof. Saswat Chakrabarti  will be added soon
5 Website/Portal (Helpdesk) Queries regarding NDLI and its services support@ndl.gov.in
6 Contents and Copyright Issues Queries related to content curation and copyright issues content@ndl.gov.in
7 National Digital Libarray of India Club (NDLI Club) Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach clubsupport@ndl.gov.in
8 Digital Preservation Centre (DPC) Assistance with digitizing and archiving copyright-free printed books dpc@ndl.gov.in
9 IDR Setup or Support Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops idr@ndl.gov.in
Cite this Content
Loading...