NDLI: Design of a flexible high-speed FPGA-based flow monitor for next generation networks

Content Provider	IEEE Xplore Digital Library
Author	McGlone, J. Woods, R. Marshall, A. Blott, M.
Copyright Year	2010
Description	Author affiliation: Xilinx Research Labs, Xilinx Inc, Dublin, Ireland (Blott, M.) \|\| ECIT, Queens University Belfast, Belfast, UK (McGlone, J.; Woods, R.; Marshall, A.)
Abstract	The evolution of new services and the development of next generation networks is placing severe demands on networks. In order to support emerging services, it is clear that a higher degree of monitoring functionality is needed within networks. One approach is to use the programmability and performance of Field Programmable Gate Array (FPGA) technology to allow distributed monitoring but this present challenges around memory usage and highlights the need for a strategically different approach to how flows are monitored. A novel FPGA-based, programmable IP flow monitor is presented, that permits various forms of network monitoring functionality, specifically monitoring of different classes of traffic, to be performed. A key aspect was to address the traditionally long design times, through the use of a new, experimental, high-level design flow called Packet Xpress which allowed functions to be quickly implemented, providing a twentyfold speed-up in design time. The monitor has been implemented on a Xilinx Virtex-5 based ML506 board and verified in hardware using real Internet traffic traces. The platform allowed us to experiment with various monitoring functions and establish their resource requirements.
Starting Page	37
Ending Page	44
File Size	455262
Page Count	8
File Format	PDF
ISBN	9781424479368
e-ISBN	9781424479382
DOI	10.1109/ICSAMOS.2010.5642096
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-19
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGAs telecomms monitoring Protocols high level design Hardware Internet IP networks Monitoring Field programmable gate arrays Next generation networking
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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