NDLI: Test processor ASIC design

Content Provider	IEEE Xplore Digital Library
Author	Ali, L. Darus, Z.M. Ali, M.A.M. Ahmed, I.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia (Ali, L.)
Abstract	In this paper, a design of a test processor ASIC employing a probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable need for every test set, signature analyzer and 3 built-in RAMs and other control circuitry. It is capable of generating random numbers and applying them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate a signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design a low cost IC tester of reliable performance.
Starting Page	261
Ending Page	265
File Size	463855
Page Count	5
File Format	PDF
ISBN	0780333888
DOI	10.1109/SMELEC.1996.616494
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-11-26
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Process design Circuit testing Linear feedback shift registers Polynomials Linear feedback control systems Feedback circuits Random number generation Electrical fault detection Fault detection
Content Type	Text
Resource Type	Article

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