NDLI: A new scalable directory architecture for large-scale multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Acacio, M.E. Gonzalez, J. Garcia, J.M. Duato, J.
Copyright Year	2001
Description	Author affiliation: Dept. Ing. y Tecnolgia de Comput., Murcia Univ., Spain (Acacio, M.E.)
Abstract	The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very large-scale systems. This work is focused on improving the scalability of shared-memory multiprocessors by significantly reducing the size of the directory. We propose multilayer clustering as an effective approach to reduce the directory-entry width. Detailed evaluation for 64 processors shows that using this approach we can drastically reduce the memory overhead, while suffering a performance degradation we similar to previous compressed schemes (such as Coarse Vector). In addition, a novel two-level directory architecture is proposed in order to eliminate the penalty caused by these compressed directories. This organization consists of a small Full-Map first-level directory (which provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides in-excess information). Results show that a system with this directory architecture can achieve the same performance as a multiprocessor with a big and non-scalable Full-Map directory with a very significant reduction of the memory overhead.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Archit
Starting Page	97
Ending Page	106
File Size	988345
Page Count	10
File Format	PDF
ISBN	0769510191
ISSN	15300897
DOI	10.1109/HPCA.2001.903255
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-19
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Scalability Broadcasting Delay Bandwidth Access protocols Computer architecture Nonhomogeneous media Degradation Multiprocessor interconnection networks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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