NDLI: Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects

Content Provider	IEEE Xplore Digital Library
Author	Artundo, I. Heirman, W. Loperena, M. Debaes, C. Van Campenhout, J. Thienpont, H.
Copyright Year	2009
Abstract	Photonic Networks-On-Chip have emerged as a viable solution for interconnecting multicore computer architectures in a power-efficient manner. Current architectures focus on large messages, however, which are not compatible with the coherence traffic found on chip multiprocessor networks. In this paper, we introduce a reconfigurable optical interconnect in which the topology is adapted automatically to the evolving traffic situation. This allows a large fraction of the (short) coherence messages to use the optical links, making our technique a better match for CMP networks when compared to existing solutions. We also evaluate the performance and power efficiency of our architecture using an assumed physical implementation based on ultra-low power optical switching devices and under realistic traffic load conditions.
Starting Page	163
Ending Page	169
File Size	508775
Page Count	7
File Format	PDF
ISBN	9780769538471
ISSN	15504794
DOI	10.1109/HOTI.2009.27
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Optical buffering Optical packet switching Optical resonators Optical interconnections Optical sensors Circuits Optical fiber networks Optical fiber communication Optical devices Parallel architectures Multiprocessor interconnection Network interfaces Optical communication Reconfigurable architectures Photonic switching systems
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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