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  1. IEEE International Workshop on Memory Technology, Design and Testing.
  2. IEEE International Workshop on Memory Technology, Design and Testing,
  3. RAM diagnostic tests
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2009 IEEE International Workshop on Memory Technology, Design, and Testing
2007 IEEE International Workshop on Memory Technology, Design and Testing
2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'06)
2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)
Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.
Records of the 2003 International Workshop on Memory Technology, Design and Testing
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing
Records of the IEEE International Workshop on Memory Technology, Design and Testing
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)
Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159)
IEEE International Workshop on Memory Technology, Design and Testing,
Memory Technology, Design and Testing
Future trends in flash memories
Recent developments in dram testing
Built in self testing for detection of coupling faults in semiconductor memories
A built in self test scheme for 256Meg sdram
Proposed on-chip test structure to quantify trap densities within flash meories
A concurrent placement and routing strategy for improving the quality of application specific memory designs
Flash memory quality and reliability issues
A low power current sensing scheme for cmos sram
Giga-bit DRAM trend
Flash memory technology - a review
Rambist builder: a methodology for automatic built-in self-test design of embedded rams
A synthesizable ram bist circuit for applying an O(n log/sub 2/ n) test that detects scrambled static pattern-sensitive faults
Methods for memory test time reduction
Design and analysis of a synchronous dram memory module
Scanning capacitance microscopy analysis of dram trench capacitors
Thermal monitoring of memories
Unexpected charge losses from the floating gates of eeprom memory cells
RAM diagnostic tests
A true testprocessor-per-pin algorithmic pattern generator
Design-for-test analysis of a buffered sdram dimm
Author index
Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Proceedings of IEEE International Workshop on Memory Technology, Design, and Test
Records of the 1993 IEEE International Workshop on Memory Testing

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RAM diagnostic tests

Content Provider IEEE Xplore Digital Library
Author Yarmolik, V.N. Klimets, Yu.V. van de Goor, A.J. Demidenko, S.N.
Copyright Year 1996
Description Author affiliation: Belarusian State University (Yarmolik, V.N.)
Abstract In this paper the following problems are considered : 1) march test's diagnostic capability estimation, ie. the type of the fault and it's location; 2) advanced march tests with diagnostic ability; 3) a march test with the same fault coverage as test March C and optimal diagnostic ability.
Starting Page 100
Ending Page 102
File Size 258205
Page Count 3
File Format PDF
ISBN 0818674660
ISSN 10874852
DOI 10.1109/MTDT.1996.782499
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 1996-08-13
Publisher Place Singapore
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Electronic equipment testing Software testing Read-write memory Random access memory Fault location Fault diagnosis Information technology Informatics State estimation Fault detection
Content Type Text
Resource Type Article
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