NDLI: Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

Content Provider	IEEE Xplore Digital Library
Author	Jiliang Zhang Yaping Lin Yongqiang Lyu Cheung, R.C.C. Wenjie Che Qiang Zhou Jinian Bian
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong, China (Cheung, R.C.C.) \|\| Coll. of Inf. Sci. & Eng., Hunan Univ., Changsha, China (Jiliang Zhang; Yaping Lin; Wenjie Che) \|\| Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing, China (Yongqiang Lyu) \|\| DCST, Tsinghua Univ., Beijing, China (Qiang Zhou; Jinian Bian)
Abstract	The continuous growth in both capability and capacity for FPGA now requires significant resources invested in the hardware design, which results in two classes of main security issues: 1) the unauthorized use and piracy attacks including cloning, reverse engineering, tampering etc. 2) the licensing issue. Binding hardware IPs (HW-IPs) to specific FPGA devices can efficiently resolve these problems. However, previous binding techniques are all based on encryption and hence have three main drawbacks: 1) encryption-based proposals in commercial are limited to protect the single large FPGA configuration, 2) many encryption-based proposals depend on a trusted third party to involve the licensing protocol, and 3) the encryption-based binding methods use costly mechanisms such as secure ROM or flash memory to store FPGA specific cryptographic keys, which is not only expensive but also vulnerable to side-channel attacks, and the management and transport of secret keys became a practical issue. In this work, we propose a PUF-FSM binding technique completely different from the traditional encryption-based methods to address these shortcomings.
Sponsorship	IEEE Comput. Soc.
Starting Page	227
Ending Page	227
File Size	128242
Page Count	1
File Format	PDF
ISBN	9781467360050
e-ISBN	9780769549699
DOI	10.1109/FCCM.2013.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Databases Licenses Cryptography Educational institutions Protocols Hardware intellectual property (IP) protection field-programmable gate array (FPGA) binding hardware designs to specific FPGA device physically unclonable functions (PUFs) finite state machine (FSM)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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