NDLI: 2.5 Gbit/s ATM switch chip set

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Deration of power dissipated in ASICs with temperature, process, and voltage variations

Simultaneous switching noise estimation for ASICs

Fast coupled noise calculation for crosstalk avoidance in MCM autorouting

Characteristics of interconnect delay in 0.5 micron CMOS

Techniques for reducing switching noise in high speed digital systems

Multiple fanout static routing network for field programmable printed circuit boards

From real-time emulation to ASIC integration for image processing applications

A comparison of FIR filter implementations based on two's complement and residue number arithmetic

Digital filter ASIC for NASA deep space radio science receiver

Split inherent-capacitive load buffer

A high-bandwidth voltage controlled oscillator (VCO) with a frequency-multiplied/divided range of 0.25-20 GHz implemented in a GaAs HBT process

A complete 0.5 /spl mu/m high performance array family

VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder

Re-engineering ASIC design with LPGAs

ASIC design for computing the Mallat's wavelet transform

VLSI implementation of discrete wavelet transform

Vector-radix IDCT implementation for MPEG decoding

Real-time integrated video-compression architecture for broadcasting HDTV and multimedia applications

Near-sensor image processing, a VLSI realization

A parallel 2 Gops/s image convolution processor with low I/O bandwidth

Bridging the gap between ASIC behavioral and structural design

VHDL code automatic generation for repetitive designs

Compiled-code VHDL approximate fault simulation

VHDL macro library testing using BOAR emulation tool

Timed dependence flow graphs, an intermediate form for verified high-level synthesis

Measuring the complexity of HDL models

A multichip module based RISC processor with programmable hardware

Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device

The physical port approach to foundry portable designs

On-chip ESD protection using capacitor-couple technique in 0.5-/spl mu/m 3-V CMOS technology

A multilayer MCM autorouter based on the correct-by-design approach

Performance-driven MCM partitioning through an adaptive genetic algorithm

Timing analysis models for gates and cells with bipolar-transistor output stages

Transient waveform response of distributed loaded RC thin film structure for voltage step function using Laplace transformation

Extraction of source/drain resistance from layout for 0.5 /spl mu/m non-salicide process technology

On the complexity of bridging fault simulation techniques for CMOS integrated circuits

Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic

A simulation tool for dynamically reconfigurable field programmable gate arrays

2.5 Gbit/s ATM switch chip set

FPGA based ATM traffic shaper for event-building networks

A single-chip, asynchronous echo canceller for high-speed data communication

High-level synthesis of control and memory intensive communication systems

NetConf: a single chip PCM conference circuit with automatic gain control, attenuation, noise suppression, soft reset and multiple frame synchronization timing

18 channel 622 Mb/s CMOS receiver array for parallel optical interconnects

GaAs ASIC for time domain reflectometer

Optimized placement of boundary scan circuitry on semi-custom ASICs

Logic vs. current testing: an evaluation using CrossCheck Technology's CM-iTest

Circuit techniques for standby mode/Iddq test compatible voltage comparators

Multiple fault simulation with random and clustered fault injection

Automatic built-in self-test insertion for high level circuit descriptions

Maximal multiple fault coverage using single fault test sets

A performance-driven macro-block placer for architectural evaluation of ASIC designs

Performance driven placement for cell-based designs

Clock driven design method (CDDM) for deep sub-micron ASICs

A systematic approach to optimizing and verifying synthesized high-speed ASICs

Testability controlled physical design of vertically stacked integrated circuits

Three-dimensional field-programmable gate arrays

A 3 V/650 MHz, 5 V/910 MHz CMOS dual modulus prescaler for low power, low input-amplitude applications

An error correction-free 10-bit 5 MHz CMOS embedded subranging A/D converter with novel bisection MSB comparators

ALAS!: an analog layout assistant for matched and balanced CMOS components

A 400 mW 50-380 MHz CMOS programmable clock recovery circuit

Full custom CMOS design and measurement of a video D/A converter

A CMOS, self calibrating, 100 MHz RC-oscillator for ASIC applications

Accurate estimation of power dissipation in CMOS sequential circuits

Efficient timing analysis using constraint-guided critical path search

Strategic evaluation of ASIC impact to electronic products

An efficient selftimed adder design

A low-cost realization of multiple-input exclusive-OR gates

Locally adaptive magnetic field detector

A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

Designing PCI bus interfaces with programmable logic

A BiCMOS read channel two-chip combo for magneto-optical disk drives

VHDL and silicon compiler experience in the advanced processor interface unit ASIC design

The MGAP-2: a micro-grained massively parallel array processor

Single chip array processor for high performance design error simulation

A design flow for embedding the ARM processor in an ASIC

High performance single chip dataflow processor

Finite state machine extraction from hardware description languages

Decompositional logic synthesis approach for look up table FPGAs

A method for timing driven datapath synthesis

High-level analog synthesis using signal flow graph transformations

A high-performance ROM compiler for 0.50 /spl mu/m and 0.36 /spl mu/m CMOS technologies

Reconfigural content addressable memory for ASIC module compiler

System design environment with synthesized blocks approach

An excursion into VHDL

VHDL synthesis techniques and recommendations

Solid-state image sensors

CCD camera design and ASIC applications

An introduction to ATM technology and its applications

Conference Author Index

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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