NDLI: Dynamic systolic associative memory chip

Content Provider	IEEE Xplore Digital Library
Author	Lipovski, G.J.
Copyright Year	1990
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA (Lipovski, G.J.)
Abstract	A dynamic random access memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (256*4096) associative memory chip based on a 1-Mb DRAM, the approximately 10 transistors per sense amplifier in a DRAM are expanded to approximately 24 transistors per sense amplifier in the modified chip. The chip size is only slightly increased, and it is manufactured using the same processes, in the same plant, as a DRAM chip; thus, it should cost about the same as a DRAM. A large array of such modified DRAMs could store a terabit database and search all of it every 60 mu s. Bit pattern searching and search-rewrite algorithms could be economically performed over very large amounts of data. The concepts and the design of the simple modified DRAM are discussed.<>
Starting Page	481
Ending Page	492
File Size	954982
Page Count	12
File Format	PDF
ISBN	0818690895
DOI	10.1109/ASAP.1990.145484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Associative memory Random access memory Costs Bandwidth Very large scale integration DRAM chips Systolic arrays Logic design Manufacturing Databases
Content Type	Text
Resource Type	Article

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