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  1. IEEE Transactions on Dependable and Secure Computing
  2. Year : 2010 Volume : 7
  3. Issue 1
  4. Using Underutilized CPU Resources to Enhance Its Reliability
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Year : 2016 Volume : 13
Year : 2015 Volume : 12
Year : 2014 Volume : 11
Year : 2013 Volume : 10
Year : 2012 Volume : 9
Year : 2011 Volume : 8
Year : 2010 Volume : 7
Issue 4
Issue 3
Issue 2
Issue 1
Editorial
Editorial
A Puzzle-Based Defense Strategy Against Flooding Attacks Using Game Theory
A Survey on the Encryption of Convergecast Traffic with In-Network Processing
Layered Approach Using Conditional Random Fields for Intrusion Detection
Secure Data Objects Replication in Data Grid
SigFree: A Signature-Free Buffer Overflow Attack Blocker
Steward: Scaling Byzantine Fault-Tolerant Replication to Wide Area Networks
Using Underutilized CPU Resources to Enhance Its Reliability
TDSC Information for authors
Year : 2009 Volume : 6
Year : 2008 Volume : 5
Year : 2007 Volume : 4
Year : 2006 Volume : 3
Year : 2005 Volume : 2
Year : 2004 Volume : 1

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Using Underutilized CPU Resources to Enhance Its Reliability

Content Provider IEEE Xplore Digital Library
Author Timor, A. Mendelson, A. Birk, Y. Suri, N.
Copyright Year 2004
Abstract Soft errors (or transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft errors still occur infrequently, they are rapidly becoming a major impediment to processor reliability. This is due primarily to processor scaling characteristics. In the past, systems designed to tolerate such faults utilized costly customized solutions, entailing the use of replicated hardware components to detect and recover from microprocessor faults. As the feature size keeps shrinking and with the proliferation of multiprocessor on die in all segments of computer-based systems, the capability to detect and recover from faults is also desired for commodity hardware. For such systems, however, performance and power constitute the main drivers, so the traditional solutions prove inadequate and new approaches are required. We introduce two independent and complementary microarchitecture-level techniques: double execution and double decoding. Both exploit the typically low average processor resource utilization of modern processors to enhance processor reliability. double execution protects the out-of-order part of the CPU by executing each instruction twice. Double decoding uses a second, low-performance low-power instruction decoder to detect soft errors in the decoder logic. These simple-to-implement techniques are shown to improve the processor's reliability with relatively low performance, power, and hardware overheads. Finally, the resulting ¿excessive¿ reliability can even be traded back for performance by increasing clock rate and/or reducing voltage, thereby improving upon single execution approaches.
Sponsorship IEEE Computer Society
Starting Page 94
Ending Page 109
Page Count 16
File Size 5229735
File Format PDF
ISSN 15455971
Volume Number 7
Issue Number 1
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2010-01-01
Publisher Place U.S.A.
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Circuit faults Decoding Hardware Fault detection Circuit noise Impedance Microprocessors Microarchitecture Resource management Power system reliability double execution. Transient faults soft errors superscalar fault tolerance microarchitecture Double Execution Soft Errors Superscalar Fault tolerance Micro-architecture
Content Type Text
Resource Type Article
Subject Electrical and Electronic Engineering Computer Science
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