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  1. Transactions on Design Automation of Electronic Systems (TODAES)
  2. ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
  3. Issue 4, September 2007
  4. Compilation for compact power-gating controls
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ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 22
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 21
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 20
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 19
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 18
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 17
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 16
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 15
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 14
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 13
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
Issue 4, September 2007
Temporal floorplanning using the three-dimensional transitive closure subGraph
Idle energy minimization by mode sequence optimization
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling
A practical dynamic single assignment transformation
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors
Techniques for the synthesis of reversible Toffoli networks
MPSoC memory optimization using program transformation
Functional verification of task partitioning for multiprocessor embedded systems
Clock skew scheduling with race conditions considered
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization
Low-Power and testable circuit synthesis using Shannon decomposition
ILP and heuristic techniques for system-level design on network processor architectures
Optimization of polynomial datapaths using finite ring algebra
Incremental hierarchical memory size estimation for steering of loop transformations
Compilation for compact power-gating controls
A note on “a mapping algorithm for computer-assisted exploration in the design of embedded systems”
Issue 3, August 2007
Issue 2, April 2007
Issue 1, January 2007
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 11
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 10
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 9
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 8
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 7
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 6
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 5
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 4
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 3
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 2
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 1

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Compilation for compact power-gating controls

Content Provider ACM Digital Library
Author You, Yi-Ping Huang, Chung-Wen Lee, Jenq Kuen
Copyright Year 2007
Abstract Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a $\textit{sink-n-hoist}$ framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.
File Format PDF
ISSN 10844309
e-ISSN 15577309
DOI 10.1145/1278349.1278364
Volume Number 12
Issue Number 4
Journal ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2007-09-01
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword Compilers for low power Balanced scheduling Data-flow analysis Leakage-power reduction Power-gating mechanisms
Content Type Text
Resource Type Article
Subject Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering
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