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  1. Transactions on Design Automation of Electronic Systems (TODAES)
  2. ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 11
  3. Issue 3, July 2006
  4. Warp Processors
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ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 22
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 21
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 20
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 19
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 18
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 17
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 16
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 15
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 14
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 13
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 11
Issue 4, October 2006
Issue 3, July 2006
Introduction to special issue: Novel paradigms in system-level design
System level design paradigms: Platform-based design and communication synthesis
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Analysis and optimization of distributed real-time embedded systems
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
Warp Processors
Module placement for fault-tolerant microfluidics-based biochips
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing
Simultaneous placement with clustering and duplication
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks
Issue 2, April 2006
Issue 1, January 2006
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 10
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 9
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 8
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 7
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 6
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 5
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 4
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 3
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 2
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 1

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Warp Processors

Content Provider ACM Digital Library
Author Lysecky, Roman Vahid, Frank Stitt, Greg
Copyright Year 2006
Abstract We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66&percent; across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications.
Starting Page 659
Ending Page 681
Page Count 23
File Format PDF
ISSN 10844309
e-ISSN 15577309
DOI 10.1145/1142980.1142986
Volume Number 11
Issue Number 3
Journal ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2004-06-07
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword FPGA Warp processors Configurable logic Dynamic optimization Hardware/software codesign Hardware/software partitioning Just-in-time (JIT) compilation
Content Type Text
Resource Type Article
Subject Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering
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