NDLI: Path delay fault testing using test points

Content Provider	ACM Digital Library
Author	Denny, N. Tragoudas, S.
Copyright Year	2003
Abstract	Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more accuracy in testing, it is proposed that test points should be inserted with the additional constraint that every path has a bounded number of test points. A polynomial time solvable integer linear programming (ILP) formulation serves as the basis for the presented test placement methodology. Due to the ILP's global optimization property we achieve results that are comparable to those by an existing greedy technique for the less constrained test point placement problem.
Starting Page	1
Ending Page	10
Page Count	10
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/606603.606604
Volume Number	8
Issue Number	1
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Automatic test pattern generation Delay testing Design for testability Path delay fault simulation (coverage) Path delay fault testing Testing digital circuits
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

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