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  1. Transactions on Design Automation of Electronic Systems (TODAES)
  2. ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 3
  3. Issue 3, July 1998
  4. Bounded-skew clock and Steiner routing
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ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 22
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 21
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 20
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 19
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 18
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 17
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 16
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 15
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 14
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 13
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 11
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 10
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 9
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 8
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 7
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 6
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 5
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 4
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 3
Issue 4, Oct 1998
Issue 3, July 1998
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
Bounded-skew clock and Steiner routing
Confidence analysis for defect-level estimation of VLSI random testing
Rate analysis for embedded systems
Optimal clock period FPGA technology mapping for sequential circuits
The edge-based design rule model revisited
Eliminating false loops caused by sharing in control path
Optimal river routing with crosstalk constraints
Issue 2, April 1998
Issue 1, Jan 1998
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 2
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 1

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Bounded-skew clock and Steiner routing

Content Provider ACM Digital Library
Author Cong, Jason Tsao, C.-W. Albert Kahng, Andrew B. Koh, Cheng-Kok
Copyright Year 1998
Abstract We study the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. Our bounded-skew routing algorithm, called the BST/DME algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a merging region. For a prescribed topology, BST/DME constructs a bounded-skew tree (BST) in two phases: (i) a bottom-up phase to construct a binary tree of merging regions which represent the loci of possible embedding points of the internal nodes, and (ii) a top-down phase to determine the exact locations of the internal nodes. We present two approaches to construct the merging regions: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the $\textit{boundaries}$ of merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and a dynamic programming-based selection technique to consider merging points that are $\textit{interior}$ to, as well as on the boundary of, the merging regions. When the topology is not prescribed, we propose a new $\textit{Greedy}-BST/DME$ algorithm which combines the merging region computation with topology generation. The Greedy-BST/DME algorithm very closely matches the best known heuristics for the zero-skew case and for the unbounded-skew case (i.e., the Steiner minimal tree problem). Experimental results show that our BST algorithms can produce a set of routing solutions with smooth skew and wire length tradeoffs.
Starting Page 341
Ending Page 388
Page Count 48
File Format PDF
ISSN 10844309
e-ISSN 15577309
DOI 10.1145/293625.293628
Volume Number 3
Issue Number 3
Journal ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 1998-07-01
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword (inter)connection Elmore delay Steiner tree VLSI Boundary merging and embedding Bounded-skew Clock tree Interior merging and embedding Low power Merging region Merging segment Pathlength delay Synchronization Zero-skew
Content Type Text
Resource Type Article
Subject Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering
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