NDLI: Realizing reconfigurable mesh algorithms on softcore arrays

Content Provider	IEEE Xplore Digital Library
Author	Giefers, H. Platzner, M.
Copyright Year	2008
Description	Author affiliation: Univ. of Paderborn, Paderborn (Giefers, H.; Platzner, M.)
Abstract	The reconfigurable mesh is a very popular model for massively parallel computation for which a large body of algorithms with exceptionally low runtime complexities exists. However, these low complexities can not be exploited due to the unrealistic assumption that communication time is either constant or logarithmic in the number of cores. Nevertheless, studying the reconfigurable mesh model and associated algorithms might lead to new approaches for the design and programming of many cores with light-weight, circuit-switched interconnects. In this paper, we present the mapping of reconfigurable mesh algorithms to softcore arrays. We first discuss our architecture and the corresponding tool flow, and then turn to the most critical issues, minimizing communication delay and establishing synchronization in the single-operand, circuit-switched network. We show experimental results from an FPGA prototype and evaluate our architecture by a sparse matrix multiplication case study.
Starting Page	41
Ending Page	48
File Size	3082408
Page Count	8
File Format	PDF
ISBN	9781424419852
DOI	10.1109/ICSAMOS.2008.4664845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Runtime Message passing Network-on-a-chip Integrated circuit interconnections Prototypes Switches Computer architecture Routing Vehicle dynamics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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