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2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)

IEEE International Interconnect Technology Conference

2013 IEEE International Interconnect Technology Conference - IITC

2012 IEEE International Interconnect Technology Conference

2011 IEEE International Interconnect Technology Conference

2010 IEEE International Interconnect Technology Conference

2009 IEEE International Interconnect Technology Conference

2008 International Interconnect Technology Conference

2007 IEEE International Interconnect Technology Conferencee

2006 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

IEEE 2000 International Interconnect Technology Conference

Technology challenges for communications systems chips

Clock distribution networks with on-chip transmission lines

An optical clock distribution network for gigascale integration

Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000)

New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

A novel via blockage model and its implications

Comparison of key performance metrics in two- and three-dimensional integrated circuits

Multi-I/O and reconfigurable RF/wireless interconnect based on near field capacitive coupling and multiple access techniques

Comparative analysis of metal and optical interconnect technology

Multilevel test structures for metal CMP integration application to Cu/SiO/sub 2/ damascene interconnect

A grain size limitation inherent to electroplated copper films

Trench and via filling profile simulations for copper electroplating process

A new hollow-cathode magnetron source for 0.10 /spl mu/m copper applications

Development of TiSiN diffusion barriers for Cu/SiLK metallization schemes

Process integration of CVD Cu as a seed layer for Cu electroplating and a plug-fill application

An evaluation of the HotOzone/sup TM/ process: a new post etch resist and residue removal process

Physical modeling of rinsing and cleaning of submicron trenches

The characterization of trimethylsilane based PE-CVD /spl alpha/-SiCO:H low-k films

Study on adhesion properties of low dielectric constant films by stud pull test and modified edge lift-off test

Effect of fluorinated plasma on SiLK during mineral hard masks etching

Preliminary study on dependency of basic properties of porous silica ILD thin film on CMP compatibility

Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices

Effect of TiCl/sub 4/ pre-treatment in PECVD-Ti process for sub-0.2 /spl mu/m metal bit line contacts

New method to study unlanded via architecture. Application to advanced interconnects: Al with low k and copper dual damascene

Comparison between HDP CVD and PECVD silicon nitride for advanced interconnect applications

Integration of low-k spin-on polymer and Cu for Damascene

Electrical reliability issues of integrating low-K dielectrics with Cu metallization

Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm

New strategy to improve the mechanical strength and to reduce potential contamination of dielectric materials for double level metal integration

Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films

Nanoscale elastic imaging: a new metrology tool for low-k dielectric integration

Characterization and integration of porous extra low-k (XLK) dielectrics

Application of high pressure process into Cu/low-k technologies

Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector

Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18 /spl mu/m mixed mode signal and system-on-a-chip (SoC) applications

Correlation of stress and texture evolution during self- and thermal annealing of electroplated Cu films

Investigation of the roles of the additive components for second generation copper electroplating chemistries used for advanced interconnect metalization

A thick-Cu process for add-on interconnections using photosensitive varnish for thick interlayer dielectric

A three-dimensional stochastic wire-length distribution for variable separation of strata

Generic models for interconnect delay across arbitrary wire-tree networks

Optimal repeater insertion for n-tier multilevel interconnect architectures

RF etch pre-clean effect on PVD Al filling with low k SiLK IMD

Ultralow k SiO/sub 2/ thin films with nano-voids by gas-evaporation technique

A super low-k (k=1.1) silica aerogel film using supercritical drying technique

Plasma treatment after interconnect metal etch for recovery of plasma charge-induced damages

Effect of W-plug via on electromigration lifetime of metal interconnect

Low-frequency noise measurement of copper damascene interconnects

0.42 /spl mu/m contacted pitch dual damascene copper interconnect for 0.15 /spl mu/m EDRAM using tapered via aligned to trench

Tungsten via poisoning caused by water trapped in embedded organic low-K dielectrics

Ultra-low dielectric constant low density material (k=2.2) for Cu damascene

The effects of substrate resistivity on RF component and circuit performance

Development of a random-walk algorithm for IC-interconnect analysis: 2D TE benchmarks, materially homogeneous domains

When should on-chip inductance modeling become necessary for VLSI timing analysis?

Electron spin resonance (ESR) characterization of defects in low-k dielectrics-temperature effect

Thickness measurement for Cu and Ta thin films using optoacoustics

Picosecond ultrasonic study of the electrical and mechanical properties of CoSi/sub 2/ formed under Ti and TiN cap layers

Film properties and surface profile after gap fill of electrochemically deposited Cu films by DC and pulse reverse processes

CVD copper thin film deposition by using (1-pentene)Cu(I)(hfac)

Microstructure evolution of electroplated Cu during room temperature transient

The evaluation of the diffusion barrier performance of reactively sputtered TaN/sub x/ layers for copper metallization

Novel post electroplating in-situ rapid annealing process for advanced copper interconnect application

Quantitative analysis on Cu diffusion through TaN barrier metal and the device degradation by using two-level Cu-interconnects implemented 0.25 /spl mu/m-256 Mbit DRAMs

Electromigration in multi-level interconnects with polymeric low-k interlevel dielectrics

The effect of residual tensile stress on electromigration lifetime of metal lines passivated by various oxides

Monte-Carlo simulation of electromigration failure distributions of submicron contacts and vias: a new extrapolation methodology for reliability estimate

A copper drift-model for the low-/spl kappa/ polymer DVS-BCB

Reliability of dual damascene Cu metallization

Integration of copper and fluorosilicate glass for 0.18 /spl mu/m interconnections

Simple, reliable Cu/low-k interconnect integration using mechanically-strong low-k dielectric material: silicon-oxycarbide

Copper dual damascene integration using organic low k material: construction architecture comparison

Half-conductive coupling interconnection technology for digital transmission between CMOS chips

Microstructure characterization of metal interconnects and barrier layers: status and future

Integration and reliability of copper magnesium alloys for multilevel interconnects

Extension of copper plating to 0.13 /spl mu/m nodes by pulse-modulated plating

CVD Cu technology development for advanced Cu interconnect applications

Inline monitoring of multi-level dual inlaid copper interconnect technologies

Cleaning process strategies compatible with low-k dielectric and copper: state of the art, evolution and perspectives

Complete-abrasive-free process for copper damascene interconnection

The investigation of galvanic corrosion in post-copper-CMP cleaning

A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric

A 7 level metallization with Cu damascene process using newly developed abrasive free polishing

Dual damascene architectures evaluation for the 0.18 /spl mu/m technology and below

Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node

An optimized integration scheme for 0.13 /spl mu/m technology node dual-damascene Cu interconnect

Copper-SiOC-AirGap integration in a double level metal interconnect

Irregular growth of PECVD-Ti silicide film on doped Si substrates

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)

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